1. Field of the Invention
The present invention relates to voltage regulation circuitry. More particularly, this invention relates to providing an output voltage in dependence on a supply voltage using pull-up and pull-down threshold devices connected between the supply voltage and a reference voltage, the threshold devices being switched in dependence on a control signal.
2. Description of the Prior Art
It is known to provide voltage regulation circuitry connected between a supply voltage node and a reference voltage node to generate an output voltage and an intermediate output voltage node, wherein threshold devices of the voltage regulation circuitry are switched in dependence on a control signal. This enables the output voltage level to be controlled in dependence on the control signal. One environment in which such a voltage regulation circuit may be used is in the context of providing a supply voltage for the bitcells of a memory array. An example known bitcell is schematically illustrated in FIG. 1A. The bitcell 10 comprises reverse coupled inverters 12 and 14, which enable a logical value to be held at each of the bitcell nodes 16 and 18. In the illustrated example a logical value “1” is held at bitcell node 16, whilst a logical value “0” is held at bitcell node 18. Each of the bitcell inverters 12 and 14 is powered by bitcell supply voltage VDDCE and connected to the reference voltage VSSE. The bitcell 10 is connected to the bitlines BL and NBL via pass gates 20 and 22, each controlled by a wordline signal WL.
A problem which can arise in such bitcells (which may for example be SRAM cells) in advanced processed technologies is that it can become difficult to write a logical “0” at a bitcell node which is holding a previously stored logical value “1”, when the bitcell is operating at the low operational voltages which are desired in contemporary integrated circuits. The occurrence of this problem is further illustrated with reference to FIG. 1B, which schematically illustrates a bitcell node 16 holding a logical value “1”. In order for this value to be rewritten as a logical value “0” the wordline generation circuitry 30 asserts the wordline signal WL controlling the pass gate 20, in order to discharge bitcell node 16 via bitline BL. However, when the pass gate 20 is relatively weak, it can be difficult for the pass gate 20 to overcome the pull-up device 24 within the bitcell.
A known solution to this problem is to temporarily lower the bitcell supply voltage VDDCE during the write process in order to make the bitcell pull-up device 24 weaker and easier to overcome. Given that such memory arrays typically make use of various self-timing signals for their operation, the usual approach is to generate a self-timed pulse for the pull-down of the bitcell supply voltage VDDCE. However, extra control circuitry must be provided in order to generate this self-timed pulse which may be skewed with respect to the main self-timed path in the memory array. Furthermore, when pulling down the bitcell supply voltage, it must be ensured that the bitcell supply voltage is not allowed to fall too low, since otherwise the bitcell contents (in particular, the contents of other bitcells sharing this bitcell supply voltage) may be corrupted. In addition there is a power and cycle time overhead associated with the bitcell supply voltage falling lower than necessary. Moreover, variability in the rate of fall of the bitcell supply voltage (due to process, temperature variation etc) means that, when generating a self-timed pulse for the pull-down, extra margin needs to be left to ensure reliable operation despite these variations. These factors make it difficult to provide a single circuit which will work across the whole range of expected process, temperature, pulse width and bitcell column size variation.
Hence it would be desirable to provide an improved technique for providing such voltage regulation circuitry.